reth_primitives_traits/
log.rs#[cfg(test)]
mod tests {
use alloy_primitives::{Address, Bytes, Log as AlloyLog, B256};
use alloy_rlp::{RlpDecodable, RlpEncodable};
use proptest::proptest;
use proptest_arbitrary_interop::arb;
use reth_codecs::{add_arbitrary_tests, Compact};
use serde::{Deserialize, Serialize};
#[derive(
Clone,
Debug,
PartialEq,
Eq,
RlpDecodable,
RlpEncodable,
Default,
Serialize,
Deserialize,
Compact,
)]
#[cfg_attr(any(test, feature = "arbitrary"), derive(arbitrary::Arbitrary))]
#[add_arbitrary_tests(compact, rlp)]
struct Log {
address: Address,
topics: Vec<B256>,
data: Bytes,
}
impl From<AlloyLog> for Log {
fn from(mut log: AlloyLog) -> Self {
Self {
address: log.address,
topics: std::mem::take(log.data.topics_mut_unchecked()),
data: log.data.data,
}
}
}
impl From<Log> for AlloyLog {
fn from(log: Log) -> Self {
Self::new_unchecked(log.address, log.topics, log.data)
}
}
proptest! {
#[test]
fn test_roundtrip_conversion_between_log_and_alloy_log(log in arb::<Log>()) {
let mut compacted_log = Vec::<u8>::new();
let len = log.to_compact(&mut compacted_log);
let alloy_log = AlloyLog::from_compact(&compacted_log, len).0;
assert_eq!(log, alloy_log.into());
let alloy_log = AlloyLog::new_unchecked(log.address, log.topics, log.data);
let mut compacted_alloy_log = Vec::<u8>::new();
let alloy_len = alloy_log.to_compact(&mut compacted_alloy_log);
assert_eq!(len, alloy_len);
assert_eq!(compacted_log, compacted_alloy_log);
}
}
}